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1 january 2001 dsc-2720/12 ?2000 integrated device technology, inc. idt7134sa/la high-speed 4k x 8 dual-port static sram features high-speed access ? military: 25/35/45/55/70ns (max.) ? industrial: 25/35/55ns (max.) ? commercial: 20/25/35/45/55/70ns (max.) low-power operation ? idt7134sa active: 700mw (typ.) standby: 5mw (typ.) ? idt7134la active: 700mw (typ.) standby: 1mw (typ.) functional block diagram i/o control i/o control memory array address decoder address decoder r/ w l oe l a 0l -a 11l i/o 0l -i/o 7l 2720 drw 01 ce l a 0r -a 11r i/o 0r -i/o 7r oe r ce r r/ w r fully asynchronous operation from either port battery backup operation?2v data retention (la only) ttl-compatible; single 5v (10%) power supply available in 48-pin dip, lcc, flatpack and 52-pin plcc military product compliant to mil-prf-38535 qml industrial temperature range (?40c to +85c) is available for selected speeds
idt7134sa/la high-speed 4k x 8 dual-port static sram military, industrial and commercial temperature ranges 2 pin configurations (1,2,3) notes: 1. all v cc pins must be connected to the power supply. 2. all gnd pins must be connected to the ground supply. 3. p48-1 package body is approximately .55 in x 2.43 in x .18 in. c48-2 package body is approximately .62 in x 2.43 in x .15 in. j52-1 package body is approximately .75 in x .75 in x .17 in. l48-1 package body is approximately .57 in x .57 in x .68 in. f48-1 package body is approxiamtely .75 in x .75 in x .11 in. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of actual part-marking. a 10r 2720 drw 02 i/o 0r i/o 1r i/o 2r i/o 3r i/o 4r i/o 5r i/o 6r i/o 7r a 9r a 8r a 7r a 6r a 4r a 3r a 2r a 1r a 0r 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 148 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a 0l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l idt7134p or c p48-1 (4) & c48-2 (4) 48-pin top view (5) ce l r/ w l oe l v cc a 5r r oe a 11r r/ w r ce r a 11l a 10l gnd , 2720 drw 03 idt7134j j52-1 (4) 52-pin plcc top view (5) index n / c g n d i / o 4 l i / o 5 l i / o 6 l i / o 7 l i / o 0 r i / o 1 r i / o 2 r i / o 3 r i / o 4 r i / o 5 r i / o 6 r oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r n/c i/o 7r 46 45 44 43 42 41 40 39 38 37 36 35 34 i/o 3l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l 8 9 10 11 12 13 14 15 16 17 18 19 20 47 48 49 50 51 52 1 2 3 4 5 6 7 33 32 31 30 29 28 27 26 25 24 23 22 21 a 0 l v c c o e l r / w l c e r r / w r c e l a 1 0 l a 1 1 l a 1 1 r a 1 0 r n / c n / c 2720 drw 04 idt7134l48 or f l48-1 (4) & f48-1 (4) 48-pin lcc/flatpack top view (5) index 6543 2 1 48 47 46 45 44 43 19 20 21 22 23 25 26 27 28 29 30 24 g n d i / o 3 l i / o 4 l i / o 5 l i / o 6 l i / o 0 r i / o 1 r i / o 2 r i / o 3 r i / o 4 r i / o 5 r i / o 7 l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r i/o 6r i/o 7r 42 41 40 39 38 37 36 35 34 33 32 31 7 8 9 10 11 12 13 14 15 16 17 18 a 0 l v c c o e l r / w l c e r r / w r c e l o e r a 1 0 l a 1 1 l a 1 1 r a 1 0 r , description the idt7134 is a high-speed 4k x 8 dual-port static ram designed to be used in systems where on-chip hardware port arbitration is not needed. this part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contention when both sides simultaneously access the same dual-port ram location. the idt7134 provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. it is the user?s responsibility to ensure data integrity when simultaneously accessing the same memory location from both ports. an automatic power down feature, controlled by ce , permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using idt?s cmos high-performance technology, these dual-ports typically operate on only 700mw of power. low-power (la) versions offer battery backup data retention capability, with each port typically consuming 200w from a 2v battery. the idt7134 is packaged on either a sidebraze or plastic 48-pin dip, 48-pin lcc, 52-pin plcc and 48-pin flatpack. military grade product is manufactured in compliance with the latest revision of mil- prf-38535 qml, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
3 idt7134sa/la high-speed 4k x 8 dual-port static sram military, industrial and commercial temperature ranges capacitance (1) (t a = +25c, f = 1.0mhz) absolute maximum ratings (1) recommended operating temperature and supply voltage (1,2) recommended dc operating conditions dc electrical characteristics over the operating temperature and supply voltage range (v cc = 5v 10%) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 10% for more than 25%of the cycle time or 10 ns maximum, and is limited to < 20ma for the period of v term > vcc +10%. 3. v term = 5.5v. notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0v to 3v and from 3v to 0v. notes: 1. this is the parameter t a . this is the "instant on" case temperature. notes: 1. v il (min.) > -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 10%. notes: 1. at vcc < 2.0v input leakages are undefined. symbol rating commercial & industrial military unit v te r m (2) terminal voltage with respect to gnd -0.5 to +7.0 -0.5 to +7.0 v t bias temperature under bias -55 to +125 -65 to +135 o c t stg storage temperature -65 to +150 -65 to +150 o c p t (3 ) power dissipation 1.5 1.5 w i out dc output current 50 50 ma 2720 tbl 01 grade ambient temperature gnd vcc military -55 o c to +125 o c0v 5.0v + 10% commercial 0 o c to +70 o c0v5.0v + 10% industrial -40 o c to +85 o c0v 5.0v + 10% 2720 tbl 03 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ 6.0 (2 ) v v il input low voltage -0.5 (1 ) ____ 0.8 v 2720 tbl 04 symbol parameter conditions (2 ) max. unit c in input capacitance v in = 3dv 11 pf c out output capacitance v out = 3dv 11 pf 2720 tbl 02 symbol parameter test conditions 7134sa 7134la unit min. max. min. max. |i li | input leakage current (1 ) v cc = 5.5v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current ce - v ih , v out = 0v to v cc ___ 10 ___ 5a v ol output low voltage i ol = 6ma ___ 0.4 ___ 0.4 v i ol = 8ma ___ 0.5 ___ 0.5 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 2720 tbl 05
idt7134sa/la high-speed 4k x 8 dual-port static sram military, industrial and commercial temperature ranges 4 dc electrical characteristics over the operating temperature and supply voltage range (1,2) (v cc = 5.0v 10%) notes: 1. 'x' in part number indicates power rating (sa or la). 2. v cc = 5v, t a = +25c for typical, and parameters are not production tested. 3. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. applies only to inputs at cmos level standby i sb3. 7134x20 com'l only 7134x25 com'l, ind & military 7134x35 com'l, ind & military symbol parameter test condition version typ. max. typ. max. typ. max. unit i cc dynamic ope rating current (both ports active) ce = v il outputs disabled f = f max (3 ) com'l sa la 170 170 280 240 160 160 280 220 150 150 260 210 ma mil & ind sa la ____ ____ ____ ____ 160 160 310 260 150 150 300 250 i sb1 standb y current (both ports - ttl level inputs) ce l and ce r = v ih f = f max (3 ) com'l sa la 25 25 100 80 25 25 80 50 25 25 75 45 ma mil & ind sa la ____ ____ ____ ____ 25 25 100 80 25 25 75 55 i sb2 standb y current (one po rt - ttl level inputs) ce "a " = v il and ce "b" = v ih active port outputs disabled, f=f max (3) com'l sa la 105 105 180 150 95 95 180 140 85 85 170 130 ma mil & ind sa la ____ ____ ____ ____ 95 95 210 170 85 85 200 160 i sb3 full standby current (both ports - cmos level inp uts) both ports ce l and ce r > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v, f = 0 (3) com'l sa la 1.0 0.2 15 4.5 1.0 0.2 15 4.0 1.0 0.2 15 4.0 ma mil & ind sa la ____ ____ ____ ____ 1.0 0.2 30 10 1.0 0.2 30 10 i sb4 full standby current (one po rt - cmos level inp uts) one port ce "a " or ce "b " > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v active port outputs disabled, f = f max (3 ) com'l sa la 105 105 170 130 95 95 170 120 85 85 160 110 ma mil & ind sa la ____ ____ ____ ____ 95 95 210 150 85 85 190 130 2720 tbl 06a 7134x45 com'l & military 7134x55 com'l, ind & military 7134x70 com'l & military symbol parameter test condition version typ. max. typ. max. typ. max. unit i cc dynamic operating curre nt (both ports active) ce = v il outputs disabled f = f max (3 ) com'l sa la 140 140 240 200 140 140 240 200 140 140 240 200 ma mil & ind sa la 140 140 280 240 140 140 270 220 140 140 270 220 i sb1 standby current (both ports - ttl level inputs) ce l and ce r = v ih f = f max (3 ) com'l sa la 25 25 70 40 25 25 70 40 25 25 70 40 ma mil & ind sa la 25 25 70 50 25 25 70 50 25 25 70 50 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih active port outputs disabled, f=f max (3) com'l sa la 75 75 160 130 75 75 160 130 75 75 160 130 ma mil & ind sa la 75 75 190 150 75 75 180 150 75 75 180 150 i sb3 full standby current (both ports - cmos le v e l inp uts) both ports ce l and ce r > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v, f = 0 (3) com'l sa la 1.0 0.2 15 4.0 1.0 0.2 15 4.0 1.0 0.2 15 4.0 ma mil & ind sa la 1.0 0.2 30 10 1.0 0.2 30 10 1.0 0.2 30 10 i sb4 full standby current (one port - cmos le v e l inp uts) one port ce "a" or ce "b" > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v active port outputs disabled, f = f max (3 ) com'l sa la 75 75 150 100 75 75 150 100 75 75 150 100 ma mil & ind sa la 75 75 180 120 75 75 170 120 75 75 170 120 2720 tbl 06b
5 idt7134sa/la high-speed 4k x 8 dual-port static sram military, industrial and commercial temperature ranges v cc ce da t are t en t ion mode 4.5v 4.5v v dr 2v v dr v ih v ih t cdr t r 2720 drw 05 data retention characteristics over all temperature ranges (la version only) v lc = 0.2v, v hc = v cc - 0.2v data retention waveform ac test conditions figure 1. ac output test load figure 2. output test load (for t lz , t hz , t wz , t ow ) *including scope and jig +5v 1250 ? 30pf 775 ? data out 2720 drw 06 , +5v 1250 ? 5pf * 775 ? data out 2720 drw 07 , notes: 1. v cc = 2v, t a = +25c, and are not production tested. 2. t rc = read cycle time. 3. this parameter is guaranteed by device characterization, but not production tested. input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 5ns 1.5v 1.5v figures 1 and 2 2720 tbl 08 symbol parameter test condition min. typ. (1 ) max. unit v dr v cc fo r data re te ntio n v cc = 2v 2.0 ___ ___ v i ccdr data retention current ce > v hc v in > v hc or < v lc mil. & ind. ___ 100 4000 a com'l. ___ 100 1500 t cd r (3 ) chip dese lect to data retention time 0 ___ ___ ns t r (3 ) operation recovery time t rc (2 ) ___ ___ ns 2720 tbl 07
idt7134sa/la high-speed 4k x 8 dual-port static sram military, industrial and commercial temperature ranges 6 notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. 'x' in part number indicates power rating (sa or la). ac electrical characteristics over the operating temperature and supply voltage (3) 7134x20 com'l only 7134x25 com'l, ind & military 7134x35 com'l, ind & military unit symbol parameter min.max.min.max.min.max. read cycle t rc re ad cycle time 20 ____ 25 ____ 35 ____ ns t aa address access time ____ 20 ____ 25 ____ 35 ns t ace chip enable access time ____ 20 ____ 25 ____ 35 ns t aoe output enable access time ____ 15 ____ 15 ____ 20 ns t oh output hold from address change 0 ____ 0 ____ 0 ____ ns t lz output low-z time (1,2) 0 ____ 0 ____ 0 ____ ns t hz output high-z time (1,2) ____ 15 ____ 15 ____ 20 ns t pu chip enable to power up time (2 ) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (2 ) ____ 20 ____ 25 ____ 35 ns 2 720 tbl 09a 7134x45 com'l & military 7134x55 com'l, ind & military 7134x70 com'l & military unit symbol parameter min.max.min.max.min.max. read cycle t rc read cycle time 45 ____ 55 ____ 70 ____ ns t aa address access time ____ 45 ____ 55 ____ 70 ns t ace chip enable access time ____ 45 ____ 55 ____ 70 ns t aoe output enable access time ____ 25 ____ 30 ____ 40 ns t oh output hold from address change 0 ____ 0 ____ 0 ____ ns t lz output low-z time (1,2) 5 ____ 5 ____ 5 ____ ns t hz output high-z time (1,2) ____ 20 ____ 25 ____ 30 ns t pu chip enable to power up time (2 ) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (2) ____ 45 ____ 50 ____ 50 ns 2720 tbl 09b
7 idt7134sa/la high-speed 4k x 8 dual-port static sram military, industrial and commercial temperature ranges timing waveform of read cycle no. 1, either side (1,2,4) timing waveform of read cycle no. 2, either side (1,3) notes: 1. timing depends on which signal is asserted last, oe or ce . 2. timing depends on which signal is de-asserted first, oe or ce . 3. r/ w = v ih . 4. start of valid data depends on which timing becomes effective, t aoe , t ace or t aa 5. t aa for ram address access and t saa for semaphore address access. address data out previous data valid data valid t oh t oh t aa (5) t rc 2720 drw 08 2720 drw 09 ce data out valid data (4) t pd t aoe (4) t ace oe t hz (2) t lz (1) t lz (1) t pu 50% 50% i cc i sb current t hz (2)
idt7134sa/la high-speed 4k x 8 dual-port static sram military, industrial and commercial temperature ranges 8 ac electrical characteristics over the operating temperature and supply voltage (5) notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. the specification for t dh must be met by the device supplying write data to the ram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 4. port-to-port delay through ram cells from writing port to reading port, refer to ?timing waveform of write with port-to-port read?. 5. 'x' in part number indicates power rating (sa or la). 6. t ddd = 35ns for military temperature range. symbol parameter 7134x20 com'l only 7134x25 com'l, ind & military 7134x35 com'l, ind & military unit min. max. min. max. min. max. writ e cycle t wc write cycle time 20 ____ 25 ____ 35 ____ ns t ew chip enable to end-of-write 15 ____ 20 ____ 30 ____ ns t aw address valid to end-of-write 15 ____ 20 ____ 30 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wp write pulse width 15 ____ 20 ____ 25 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 15 ____ 15 ____ 20 ____ ns t hz output high-z time (1,2) ____ 15 ____ 15 ____ 20 ns t dh data ho ld time (3 ) 0 ____ 0 ____ 3 ____ ns t wz write enable to output in high-z (1,2) ____ 15 ____ 15 ____ 20 ns t ow output active from end-of-write (1 , 2,3 ) 3 ____ 3 ____ 3 ____ ns t wdd write pulse to data delay (4 ) ____ 40 ____ 50 ____ 60 ns t dd d write data valid to read data delay (4,6) ____ 30 ____ 30 ____ 35 ns 2 720 tbl 10a symbol parameter 7134x45 com'l & military 7134x55 com'l, ind & military 7134x70 com'l & military unit min. max. min. max. min. max. writ e cycle t wc write cycle time 45 ____ 55 ____ 70 ____ ns t ew chip enable to end-of-write 40 ____ 50 ____ 60 ____ ns t aw address valid to end-of-write 40 ____ 50 ____ 60 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wp write pulse width 40 ____ 50 ____ 60 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 20 ____ 25 ____ 30 ____ ns t hz output high-z time (1,2) ____ 20 ____ 25 ____ 30 ns t dh data ho ld time (3 ) 3 ____ 3 ____ 3 ____ ns t wz write enable to output in high-z (1,2) ____ 20 ____ 25 ____ 30 ns t ow output active from end-of-write (1 , 2,3 ) 3 ____ 3 ____ 3 ____ ns t wdd write pulse to data delay (4 ) ____ 70 ____ 80 ____ 90 ns t dd d write data valid to read data delay (4,6) ____ 45 ____ 55 ____ 70 ns 2720 tbl 10b
9 idt7134sa/la high-speed 4k x 8 dual-port static sram military, industrial and commercial temperature ranges 2720 drw 10 r/ w "a" (1) valid t wc match valid match t wp t dw t wdd t ddd addr "a" data in "a" data out "b" addr "b" t aw timing waveform of write cycle no. 1, r/ w controlled timing (1,5,8) timing waveform of write with port-to-port read (1,2,3) notes: 1. write cycle parameters should be adhered to, in order to ensure proper writing. 2. ce l = ce r = v il. oe "b" = v il. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". notes: 1. r/ w or ce must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a ce =v il and r/ w = v il . 3. t wr is measured from the earlier of ce or r/ w going to v ih to the end-of-write cycle. 4. during this period, the i/o pins are in the output state, and input signals must not be applied. 5. if the ce = v il transition occurs simultaneously with or after the r/ w = v il transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal ( ce or r/ w ) is asserted last. 7. this parameter is guaranteed by device characterization, but is not production tested. transition is measured 0mv from steady state with the output test load (figure 2). 8. if oe = v il during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe = v ih during an r /w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . ce 2720 drw 11 t aw t as (6) t dw data in address t wc r/ w t wp data out t wz (7) (4) (4) (2) oe t hz (7) t lz (7) t hz t wr (3) (7) t dh t ow
idt7134sa/la high-speed 4k x 8 dual-port static sram military, industrial and commercial temperature ranges 10 truth table i ? read/write control functional description the idt7134 provides two ports with separate control, address, and i/o pins that permit independent access for reads or writes to any location in memory. these devices have an automatic power down feature controlled by ce . the ce controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected ( ce high). when a port is enabled, access to the entire memory array is permitted. each port has its own output enable control ( oe ). in the read mode, the port?s oe turns on the output drivers when set low. non-contention read/write conditions are illustrated intruth table i. timing waveform of write cycle no. 2, ce controlled timing (1,4) notes: 1. r/ w or ce must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a ce =v il and r/ w = v il . 3. t wr is measured from the earlier of ce or r/ w going high to the end-of-write cycle. 4. if the ce low transition occurs simultaneously with or after the r/ w low transition, the outputs remain in the high-impedance state. 5. timing depends on which enable signal ( ce or r/ w ) is asserted last. note: 1. a 0l - a 11l a 0r - a 11r "h" = v ih , "l" = v il , "x" = don?t care, and "z" = high impedance left or right port (1 ) r/ w ce oe d 0-7 function x h x z port deselected and in power-down mode, i sb2 or i sb4 xhx z ce r = ce l = h, power down mode i sb1 or i sb3 llx data in data o n p ort writte n into me mory hl ldata out data in memory output on port x x h z high impedance outputs 2720 tbl 1 1 2720 drw 12 r/ w t wc address data in ce t dw t wr (3) t dh t ew (2) t aw t as (5)
11 idt7134sa/la high-speed 4k x 8 dual-port static sram military, industrial and commercial temperature ranges ordering information 2720 drw 13 idt xxxx a 999 a a device type power speed package process/ temperature range blank i (1) b p c j l48 f 20 25 35 45 55 70 la sa 7134 commercial (0 cto+70 c) industrial (-40 cto+85 c) military (-55 cto+125 c) compliant to mil-prf-38535 qml 48-pin plastic dip (p48-1) 48-pin ceramic dip (c48-2) 52-pin plcc (j52-1) 48-pin lcc (l48-1) 48-pin ceramic flatpack (f48-1) speed in nanoseconds low power standard power 32k (4k x 8-bit) dual-port ram commercial only commercial, industrial & military commercial, industrial & military commercial & military commercial, industrial & military commercial & military the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 3/25/99 initiated datasheet document history converted to new format cosmetic and typographical corrections pages 2 added additional notes to pin configurations 6/9/99: changed drawing format 10/1/99: added industrial temperature ranges and removed corresponding notes 11/10/99: replaced idt logo 12/22/99: page 1 made corrections to drawing 3/3/00: corrected block diagram and pin configurations changed 500mv to 0mv 1/12/00: pages 1 and 2 moved "description to page 2 and adjusted page layout page 1 added "la only)" to paragraph page 2 fixed p48-1 package description page 3 increased storage temperature parameters clarified t a parameter page 4 dc electrical parameters?changed wording from "open" to "disabled" page 10 fixed truth table specification in "functional description" paragraph corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com

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